library ieee;
use ieee.std_logic_1164.all;

entity mux2_tb is
end mux2_tb;

architecture behav of mux2_tb is
    component mux2
        generic(n: integer);
        port(
        d0, d1: in std_logic_vector(n downto 0);
        s: in std_logic;
        y: out std_logic_vector(n downto 0)
        );
    end component;

    signal d0_s, d1_s, y_s: std_logic_vector(31 downto 0);
    signal s_s: std_logic;

begin
    M0: mux2
        generic map(31)
        port map(d0_s, d1_s, s_s, y_s);
    process
    begin
        d0_s <= x"eeeeeeff";
        d1_s <= x"ffffffee";
        s_s <= '0';
        wait for 1 ns;
        assert y_s = d0_s;

        d0_s <= x"000000ff";
        d1_s <= x"ffffff00";
        s_s <= '1';
        wait for 1 ns;
        assert y_s = d1_s;
    end process;
end behav;
